SOI substrates are composed of a silicon oxide (SiO2) layer buried between a bulk silicon substrate and thin silicon layer. These substrates are intended to be used in the fields of electronics, optics or optoelectronics.
An example of a process for fabricating an SOI substrate is disclosed in U.S. Patent Application No. 2003/0181001. The disclosed process involves ion implantation into a surface-oxidized substrate and delamination of the wafer. This substrate is then bonded to a support and then an annealing operation is carried out at temperatures between 400° C. and 600° C. to detach a portion of the substrate.
To reduce the roughness of the newly exposed portion of the substrate, a finishing annealing operation is then carried out in an atmosphere containing hydrogen, an inert gas, or a mixture of the two gases, at a temperature between 1100° C. and 1350° C. This temperature range is chosen to limit the annealing time and to avoid any contamination by impurities, such as heavy metals.
US 2003/0181001 specifies that heat treatment is carried out by annealing for a time between 10 minutes and 8 hours, or by a technique known to those skilled in the art as RTA (rapid thermal annealing). In the latter case, this process is carried out in an RTA annealing apparatus that allows temperature increases of greater than 10° C./s, and relatively short annealing times of around 30 seconds to 1 minute. Finally, this annealing step may be followed by a sacrificial oxidation step.
The process described in US 2003/0181001 has several drawbacks, namely the partial dissolution of the buried oxide layer and the lack of homogeneity in the reduction in roughness of the silicon active layer. Annealing for several hours at the proposed temperature ranges, which may be up to 1350° C., results in at least partial dissolution of the buried silicon oxide (SiO2) layer, by diffusion of the oxygen forming the silicon dioxide and by evaporation of this oxygen at the surface of the silicon active layer. For high annealing temperatures above about 1200° C., the dissolution phenomenon is also linked with the increase in solubility of oxygen in silicon and consequently its dissolution in the bulk substrate and the silicon active layer. This effect is even more pronounced for thin silicon layers with a thickness of 150 nanometers or less. In addition, the diffusion of oxygen is not homogeneous through the active layer. Consequently, the SOI substrate obtained has a buried oxide layer of poorly controlled thickness due to the diffusion phenomenon. Also, the thickness of the oxide layer is not uniform over the entire surface of the substrate.
Tests have been carried to measure these drawbacks. The results are plotted in the appended FIG. 1, which shows on the y-axis the thickness ESiO2 of the buried silicon dioxide layer of an SOI substrate after thermal annealing, and on the x-axis the average thickness ESi of the silicon active layer before annealing. The thicknesses are expressed in nanometers. Curves a, b and c represent the results obtained after annealing at temperatures of 1100° C., 1150° C. and 1200° C., respectively.
Additional results are plotted FIG. 2. The y-axis represents the change in standard uniformity ΔSiO2 as a result of annealing the buried silicon dioxide layer and x-axis represents the thickness ESi of the silicon active layer before annealing, expressed in nanometers. Curves d, e and f represent the results obtained after annealing at temperatures of 1100° C., 1150° C. and 1200° C., respectively. An annealing operation at, for example, 1200° C. is an operation during which the temperature gradually rises over several hours and is then held for 5 minutes at 1200° C.
As may be seen in FIG. 1, the higher the annealing temperature, the thinner the buried SiO2 layer. Moreover, the thinner the silicon active layer, the greater the reduction in the thickness of the buried silicon layer, especially for annealing above 1100° C. Thus, after annealing at 1200° C. (see curve c) and for silicon active layer thicknesses greater than 200 nanometers, a reduction in the thickness of the SiO2 of around 6 nanometers (compared with curve a) is observed, as shown in FIG. 2.
The term thickness uniformity denotes the maximum deviation in thickness of the buried SiO2 layer within the SOI wafer. A uniformity of 1 to 1.5 nm for a buried SiO2 layer with an average thickness of 145 nm is acceptable and commonplace. Moreover, the change in thickness uniformity of the final product corresponds to the change between the thickness uniformity values measured before and after the annealing, respectively. The 0% value of the change in uniformity in FIG. 2 indicates no change in thickness uniformity; the uniformity remains the same as that of the buried SiO2 layer before the annealing. So, an SiO2 layer whose thickness before annealing was 145 nm, a change of thickness of about 1 to 1.5 nm is a 0% change.
For a silicon active layer with a thickness of 100 nanometers or less, however, the reduction in the thickness of the buried SiO2 layer exceeds 10 nanometers (see FIG. 1). The change in uniformity may be up to 500%, as shown in curve f, having an initial uniformity value of 1 to 1.5 nm, rising to 5 to 7.5 nm after annealing. FIG. 2 also shows that this phenomenon, illustrating that the loss in thickness uniformity of the buried oxide layer is even greater for SOI substrates having a silicon active surface layer less than 60 nm. This dissolution phenomenon is more problematic the thinner the silicon dioxide (SiO2) layer is.
Another drawback of this prior art process is that annealing carried out on a surface directly after it has been debonded is much less effective than annealing carried out after a prior thinning step.
U.S. Pat. No. 6,372,609 discloses a process for fabricating an SOI substrate that includes the steps of detaching and transferring a silicon layer that has been formed by the implantation of hydrogen ions. According to this process, the finishing requires sacrificial oxidation, deoxidation of the sacrificial silicon layer, and then heat treatment in a reducing atmosphere, specifically RTA (rapid thermal annealing) at 1000° C. to 1300° C. for 1 to 60 seconds. The process disclosed in U.S. Pat. No. 6,372,609 involves heat treatment of an SOI substrate where the silicon surface layer has a thickness of at least 230 nanometers.
However, when an SOI substrate is desired with a silicon surface layer of less that 200 nm, the process becomes far more difficult, due to the challenges discussed above. The solutions of the prior art do not address these challenges. Accordingly, there is a need in the art for a process for fabricating an SOI substrate in which the silicon surface layer has a thickness less than 200 nanometers, preferably less than 150 nm, and a buried oxide layer having a uniform thickness, wherein the buried oxide layer is also thin.